An example of a conventional power supply circuit having an inverter circuit for charging a battery is described in U.S. Pat. No. 5,333,104. FIG. 8 is a circuit diagram showing the circuit configuration of this conventional technology. In FIG. 8, the inverter circuit is configured as follows:
An LC resonance circuit having a resonance capacitor C.sub.1 and a primary winding L.sub.1 connected in parallel, a parallel circuit formed of a diode D.sub.1 and a resistor R.sub.1, and a field effect transistor (FET) Q.sub.1 which is a voltage driven type switching element FET, are connected to form a series circuit. This series circuit is connected to a direct current (DC) voltage source E. Another series circuit formed with a resistor R.sub.2 and a capacitor C.sub.2 is also connected to the DC voltage source E. A feedback winding L.sub.3 connects to a connection point between the resistor R.sub.2 and the capacitor C.sub.2 and a gate of the FET Q.sub.1. The feedback winding L.sub.3 magnetically couples with the primary winding L.sub.1 forming an oscillation transformer T. Further, the connection point of the resistor R.sub.2, the capacitor C.sub.2 and the primary winding L.sub.1 is connected to another connection point of the primary winding L.sub.1 and the diode D.sub.1 through a series circuit formed of a resistor R.sub.3 and a diode D.sub.2. The resistors R.sub.2 and R.sub.3, the capacitor C.sub.2, and the diode D.sub.2 function as an oscillation drive circuit, a bias circuit, as well as a bias control circuit for achieving an oscillation of the inverter circuit with high stability.
A secondary winding L.sub.2 of the transformer T has a center tap and magnetically connects to the primary winding L.sub.1 to generate a secondary output signal. Both terminals of the secondary winding L.sub.2 connects to a positive pole of a battery B to be charge through diodes D.sub.3 and D.sub.4. The center tap of the secondary winding L.sub.2 connects to a negative pole of the battery B. By this arrangement of the inverter circuit, the secondary output signal charges the battery B.
In operation, when supplying the DC voltage E to the inverter circuit, the capacitor C.sub.2 is charged by a current I.sub.S1 flowing through the resistor R.sub.2. As a result, the voltage across the capacitor C.sub.2 increases and reaches a threshold voltage of the FET Q.sub.1. Then, the FET Q.sub.1 becomes active and goes to ON which causes a current IL.sub.1 of FIG. 9B to flow through the primary winding L.sub.1. The current IL.sub.1 through the primary winding L.sub.3 induces a voltage across the feedback winding L.sub.3 which establishes a positive feedback to initiate an oscillation in the inverter circuit.
During the period when the voltage of the capacitor C.sub.2 is lower than a drain voltage V.sub.D of the FET Q.sub.1, the charge in the capacitor C.sub.2 will be discharged by a discharge current I.sub.S2 of FIG. 8 flowing through a loop formed of the resistor R.sub.3, the diode D.sub.2, the parallel circuit of the resistor R.sub.1 and the diode D.sub.1, the FET Q.sub.1, and the capacitor C.sub.2 . Because of this discharge, the voltage of the capacitor C.sub.2 decreases below the threshold voltage of the FET Q.sub.1, which shortens the ON period of the FET Q.sub.1. However, the current I.sub.S2 discharging the capacitor C.sub.2 decreases because of the shortened period of the ON state of the FET Q.sub.1, which increases the voltage of the capacitor C.sub.2. This negative feedback relationship stabilizes a bias voltage V.sub.G2 (the voltage of the capacitor C.sub.2) as shown in FIG. 9G, resulting a highly stabilized self-induced oscillation in the inverter circuit.
FIG. 9A is a waveform diagram showing a voltage V.sub.C across the resonance capacitor C.sub.1 and FIG. 9B is a waveform diagram showing the current IL.sub.1 flowing through the primary winding L.sub.1. FIG. 9C shows a voltage V.sub.F at the connection point of the diode D.sub.1 and the LC resonant circuit formed of the capacitor C.sub.1 and the primary winding L.sub.1. The diode D.sub.1 inhibits a reverse current flowing through stray diodes of the FET Q.sub.1.
In the conventional example of FIG. 8, at the gate of the FET Q.sub.1, a sinusoidal voltage V.sub.G is induced by the feedback winding L.sub.3 as shown in FIG. 9F. The peak of the voltage V.sub.G is in the range of the threshold voltage V.sub.TH of the FET Q.sub.1. A drain current I.sub.D of FIG. 9E starts flowing through the FET Q.sub.1 even before the drain voltage V.sub.D of FIG. 9D reaches zero volt. Further, the drain current I.sub.D does not reach a zero level even when the drain voltage V.sub.D departs from the zero volt. Because of this drain current I.sub.D, switching loss results in the FET Q.sub.1.